The present invention relates generally to the field of microprocessors and computer systems. More particularly, the present invention relates to a method and apparatus for a VCC adaptive dynamically variable frequency clock system for microprocessors.
In recent years, the price of personal computers (PCs) have rapidly declined. As a result, more and more consumers have been able to take advantage of newer and faster machines. Computer systems have become increasingly pervasive in our society. But as the speed of the new processors increases, so does the power consumption. Furthermore, high power consumption can also lead to thermal issues as the heat has to be dissipated from the computer system. One popular way to reduce power is to lower the operating voltage of the devices. However, the circuitry becomes more susceptible to any voltage droops and other transients.
A high clock frequency is one of the principal performance drivers for a high performance microprocessor design. One common method for achieving higher performance is to increase the processor operating frequency. But as semiconductor process technology continues to scale and improve, the integrated circuit designs need to be optimized to track the device scaling trends and to meet new power reduction requirements. The device specifications detailing 5 volt VCC supply voltages from earlier times are making way for the more recent specifications outlining 1 volt and even sub 1 volt VCC ranges. While the aggressive scaling of operating voltages has worked towards achieving these criteria, supply voltage issues have arisen in their place.
Power is linearly proportional to the operating frequency (i.e. Powerxe2x88x9dFrequencyxc2x7Voltage2). Thus power dissipation can be lowered by decreasing the operating frequency at selected times. Similarly, the reduction of the VCC voltage leads to reduced power dissipation as power is directly proportional to the VCC level wherein powerxe2x88x9dVCC2. Furthermore, these voltage reductions are often implemented in conjunction with aggressive frequency techniques in order to optimizing performance.
Frequency/voltage adjustment methods can be used to alter the circuit performance. However, modifications to a core clock signal during processor operation can cause errors to the system. Typically, existing frequency adjustment schemes need to stop or pause the processor core before adjusting the clock frequency or modifying the bus ratio. Frequencies are changed in a clocked device by placing the device in an idle state, changing the core clock frequency to the new frequency, and locking the PLL in phase with the new frequency. The length of the idle state required for the changing and locking to occur slows down the system. Such a pause can have a significant impact on the overall performance of a desktop or server.